Power management override for portable computers

ABSTRACT

Method and apparatus for selectively overriding a prepackaged power management driver of a portable personal computer so that data transmitted to the CPIU of the computer by a device, such as a “real time” serial communicators device connected thereto, is not lost during the CPUs latency “wake up” period following a CPU power-down operation. An override system stored in memory comprises an override flag which may be set or cleared by a user or the computer. If the override flag is set, then the power management system is prevented from reducing power to the CPU so that the occurrence of a CPU latency period and thus potential for loss of data is avoided.

TECHNICAL FIELD

The invention relates generally to power management systems for personalcomputers and, more particularly, to a method and apparatus foroverriding selected aspects of such power management systems.

BACKGROUND OF THE INVENTION

Portable personal computers (PCs) were first introduced in the early1980s and have since enjoyed great commercial success and consumeracceptance. As the portable PC market has grown, users have begun todemand lighter weight, lower volume PCs which can be used for longerperiods of time between battery charges. Meeting these demands hasproved challenging in view of the fact that most portable PCs nowsupport peripheral devices previously available only on desktop PCs. Theadditional peripherals greatly increase overall power consumption,making it difficult to achieve an optimal level of functionality whilemaintaining an acceptable battery life. Furthermore, it has also becomedesirable to more efficiently manage the power consumption ofnon-battery powered desktop PCs in order to minimize overall operatingcosts.

One solution has been to design into the computer's basic input/outputsystem (BIOS) a pre-packaged power management routine, or to load intothe computer's operating system (OS) a pre-packaged driver, such as theMicrosoft™/Intel™ Advanced Power Management (APM) driver, that regulatesthe application of power to certain devices by placing such devices inan “idle” state when demand for such devices is low. For example, whendie central processing unit (CPU) is not executing a program, its powerconsumption can be reduced considerably by decreasing the speed at whichit operates. Further examples include turning off the LCD backlight orblanking the monitor screen after a period of keyboard inactivity andstopping the hard-disk drive motor after the drive has not been accessedfor a preset internal of time.

Once the power to the CPU, an I/O device, or other peripheral device isreduced the device can be powered back up if there is a demand for thatdevice. The device though does not “wake up,” i.e., regain its fullcapabilities, instantly, but rather requires a finite amount of time, or“latency,” to do so.

A problem with power management systems, as they are currentlyavailable, is that important data may be lost during the latency of theCPU when data is initially transmitted to it Specifically, such a lossof data can result when the CPU is connected to critical, “real-time”devices such as serial peripheral I/O devices, including instrumentationinterfaces, modems, and PCMCIA controllers, that transmit data seriallyto the CPU. These devices typically include a buffer for storing alimited number of bytes of data to be transmitted to the CPU. Once thebuffer is full, the stored bytes are overwritten by new incoming bytesof data It can be appreciated that bytes of data can thus be stored inthe buffer for only a limited amount of time, and if that time is lessthan the latency of the CPU, then data will be lost.

The latency problem may be avoided by selectively disabling thecomputer's power management system. Most conventional power managementsystems, prepackaged with available computer operating systems, have thecapability to selectively enable and disable their power managementfunctions. However, this defeats the purpose of the power managementsystem because all devices would then utilize full power and the userwould forfeit the advantages of power management. While some suchsystems can be operated by the user to selectively disable only certaindevices, many do not have this capability and, in particularly, cannotbe operated to disable power management functions with respect to theCPU only, while remaining enabled for the other devices.

What is needed, therefore, is a system for overriding, the operation ofa computer's prepackaged power management system that disables powermanagement functions of the CPU only, without disabling power managementfor other devices, to thereby solve the CPU latency problem when a powermanaged computer is operated in connection with serial data devices.

SUMMARY OF THE INVENTION

The foregoing problems are solved and a technical advance is achieved bya system and method for selectively disabling the existing powermanagement functions of a computer with respect to the CPU only, withoutdisabling the other power management functions of the computer, so thatthe CPU does not experience latency in being reactivated to receive datatransmitted from a device connected thereto. In a departure from theart, a power management override system is stored in the computer'smemory that controls a CPU idle override flag. If set, the flag preventsthe power management system of the computer from reducing the power tothe CPU.

In a preferred embodiment, a system is disclosed for managing the powerefficiency of a computer having a memory, a processor, and one or morepower consuming devices; wherein the computer is to be operativelyconnected to a critical input/output (I/O) device requiring theprocessor to be fully powered when transmitting data to the processor.The system comprises a power management system stored in the memory forselectively controlling the power consumption of the processor and thepower consuming devices between operation in full power and reducedpower consumption states.

The system further comprises an override system stored in the memory foroverriding the power management system to prevent the processor frombeing operated in the reduced power consumption stare yet withoutpreventing the power consuming devices from being operated in thereduced power consumption state. The power management override systemincludes a CPU idle override flag which may be set or cleared to enableor disable, respectively, the power management system. If the overrideflag is clear, then the override system is disabled, thereby permittingthe power management system to execute instructions for reducing powerto the CPU. If, however, the override flag is set, then the overridesystem is enabled and the power management system is prevented fromexecutive instructions for reducing power to the CPU. In a first aspectof the present invention, a user may selectively enable or disable theoverriding by setting or clearing, respectively, the override flag. In asecond aspect of the invention, the processor may selectively enable theoverriding automatically by setting the override flag when the criticalI/O device is actively connected to the computer, and disable itotherwise.

A technical advantage achieved with the present invention is that,because the power management of the CPU can be selectively disabled, theCPU can be prevented from experiencing a CPU latency or “wake up”period, thereby avoiding the problem of losing data that may have beentransmitted during that period.

Another technical advantage achieved with the invention is that powermanagement of the CPU may be selectively disabled without shutting downthe entire computer system or disabling power management to other systemdevices.

Yet another technical advantage achieved with the invention is that itis operable without requiring that pre-packaged power management drivercode be rewritten or even modified. Accordingly, the present inventionis readily adaptable for use with a number of different prepackagedpower management drivers.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram of a personal computer embodyingfeatures of the power management override system of the presentinvention; and

FIG. 2 is a flowchart of the logic implemented by the power managementoverride system in the system of FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 is a functional block diagram of a personal computer (PC) 10embodying features of the present invention. The PC 10 comprises acentral processing unit (CPU) 12 connected via a host bus 14 to a systemRAM 16 and a number of I/O devices collectively designated by thereference numeral 18. The I/O devices 18 may include for example, serialcommunication devices 20, PCMCIA controllers 22, a display (not shown),a keyboard (not shown), a disk drive (not shown), and a pointing devicesuch as a mouse (not shown). The PC 10 further includes an operatingsystem (OS) 24 which is stored in the system RAM 16. A power managementsystem providing standard power management routines such theMicrosoft/Intel APM driver, designated by the reference numeral 26, isalso stored in the RAM 16.

According to the invention, a power management system override system 28is stored in the RAM 16. The system 28 includes a user flag 30 and asystem flag 32, for reasons discussed in detail below. As explainedbelow, the system 28 is used to override the power management system 26so that power management functions are disabled with respect to the CPU12 only, but not disabled with respect to other power-managed devices.

FIG. 2 illustrates a flowchart of the operation of the system 28.Execution automatically begins at step 200 upon initiation of theoperating system 24 of the PC 10. In step 210, a determination is madewhether the power management system 26 has issued an instruction toplace the CPU 12 in an idle state, i.e., to “power down” the CPU.Typically, the power management system 26 will issue such an instructionwhen there is a predetermined period of CPU 12 inactivity, for instancewhen the CPU is not executing a program and may be powered down to an“idle” state. If, in step 210, a CPU idle instruction has not beenissued, execution remains at step 210. If, in step 210, a CPU idleinstruction has been issued, execution proceeds to step 220.

In step 220, the override system 28 determines whether the user overrideflag 30 is set or is cleared. The user may set or clear the overrideflag 30 using conventional computer interface techniques. If, in step220, the user override flag 30 has been set, execution returns to step210. If, in step 220, the user override flag 30 has not been set, i.e.,it is clear, execution proceeds to step 230.

In step 230, the override system 28 determines whether the deviceoverride flag 32 is set or is cleared. The device override flag 32 iscleared under normal operating conditions of the operating system 24.However, the flag 32 is set if a “critical” device is activated on thesystem. As used here, a “critical” device is any device which mayrequire service of an event by the CPU 12 during the CPU's latency “wakeup” period wherein loss of such data due to the latency would beunacceptable. Examples of such critical devices include one or moreserial communications devices 20 and the PCMCIA controller 22. If, instep 230, the device override flag 32 has been set, execution returns tostep 210. If, in step 230, the device override flag 32 has not been set,i.e., it is clear, execution proceeds to step 240 in which power to theCPU 12 is reduced or even removed totally. This is accomplished in aconventional manner such as by controlling the CPU clock speed.

In step 250, the override system 28 determines whether an interruptrequest (IRQ) has been issued to the CPU 12. If, in step 250, an IRQ isnot issued, execution remains at step 250. If, in step 250, an IRQ isissued, execution proceeds to step 260 in which the CPU is powered upfor operation, and execution then returns to step 210.

It is understood that the present invention can take many forms andembodiments. The embodiments shown herein are intended to illustraterather than to limit the invention, it being appreciated that variationsmay be made without departing from the spirit or the scope of theinvention. For example, an override system similar to the system 28described herein could be implemented for non-CPU devices of the PC 10,such as the hard disk drive. In addition, other criteria, such as timeof inactivity, could be used to set or clear the device flag 32.

Although illustrative embodiments of the invention have been shown anddescribed, a wide range of modification, change and substitution isintended in the foregoing disclosure and in some instances some featuresof the present invention may be employed without a corresponding use ofthe other features. Accordingly, it is appropriate that the appendedclaims be construed broadly and in a manner consistent with the scope ofthe invention.

What is claimed is:
 1. A system for managing the power efficiently of a computer having a memory, a processor and one or more power consuming devices, said computer to be operatively connected to a critical input/output (I/O) device requiring said processor to be fully powered when transmitting data to said processor, the system comprising: the critical device coupled to the processor for service of an event by the processor; a power management system stored in said memory for selectively controlling the power consumption of said processor and said power consuming devices between operation in full power and reduced power consumption states; and an override system coupled to determine whether an interrupt request has been issued to request a power up to the processor, the override system being stored in said memory for overriding said power management system to disable power management functions with respect to the processor only, without disabling power management with respect to the power consuming devices.
 2. The system of claim 1 wherein said overriding is enabled or disabled at the selection of a user.
 3. The system of claim 1 wherein said overriding is enabled automatically when said critical I/O device is actively connected to said computer and otherwise is disabled.
 4. The system of claim 1 wherein said override system comprises: an override flag stored in said memory, which flag may be set or cleared; means for determining whether said power management system has issued an instruction for reducing power to said processor; means responsive to a determination that said instruction for reducing power has been issued for determining whether said override flag has been set; means responsive to a determination that said override flag has been set for preventing execution of said instruction for reducing power to said processor; and means responsive to a determination that said override flag has not been set for permitting execution of said instruction for reducing power to said processor.
 5. The system of claim 1 wherein said critical I/O device is a data communication device.
 6. The system of claim 1 wherein said critical I/O device is a PCMCIA controller.
 7. A method for managing the power efficiency of a computer having a memory, a processor and one or more power consuming devices, said computer to be operatively connected to a critical input/output device requiring said processor to be fully powered when transmitting data to said processor, the system comprising: coupling the critical device to the processor for servicing of an event by the processor; selectively controlling the power consumption of said processor and said power consuming devices between operation in full power and reduced power consumption states; coupling an override system to determine whether an interrupt request has been issued to request a power up of the processor; and overriding said controlling to disable power management functions with respect to the processor only, without disabling power management with respect to the power consuming devices.
 8. The method of claim 7 wherein said overriding is enabled or disabled at the selection of a user.
 9. The method of claim 7 further comprising: determining whether said critical I/O device is actively connected to said computer: responsive to a determination that said critical I/O device is actively connected to said computer, automatically enabling said overriding: and responsive to a determination that said critical I/O device is not actively connected to said computer, automatically disabling said overriding.
 10. The method of claim 7 wherein said overriding comprises: determining whether said power management system has issued an instruction for reducing power to said processor: responsive to a determination that said instruction for reducing power has been issued, determining whether an override flag has been set; responsive to a determination that said override flag has been set, preventing execution of said instruction for reducing power to said processor, and responsive to a determination that said override flag has not been set, permitting execution of said instruction for reducing power to said processor.
 11. A method for selectively preventing a power management (PM) system stored in the memory of a computer from reducing power to a processor of said computer, while permitting said PM system to manage power to at least one other device in said computer, the method comprising: coupling the at least one other device to the processor for servicing of an event by the processor; storing in said memory at least one override flag which may be set or cleared; determining whether said PM system has issued an instruction for reducing power to said processor; coupling the at least one override flag to determine whether an interrupt request has been issued to request a power up of the processor; responsive to a determination that said instruction has been issued, determining, for each said at least one override flag, whether said at least one override flag has been set; responsive to a determination that one of said at least one override flag has been set, overriding said instruction thereby preventing power to said processor from being reduced; and responsive to a determination that none of said at least one override flag has been set, permitting power only to said processor to be reduced without disabling power management with respect to the at least one other device.
 12. The method of claim 11 wherein said at least one flag comprises a first flag that may be set or cleared by a user.
 13. The method of claim 11 wherein said at least one flag comprises a second flag that may be set or cleared by said processor, and the method further comprises determining whether a selected peripheral device is electrically connected to said processor and, responsive to a determination that a selected peripheral device is electrically connected to said processor, setting said second flag and, responsive to a determination that a selected peripheral device is not electrically connected to said processor, clearing said second flag.
 14. The method of claim 13 wherein said selected device is a communication device.
 15. The method of claim 13 wherein said selected device is a serial data communication device.
 16. The method of claim 13 wherein said selected device is a PCMCIA controller.
 17. A computer system comprising: a CPU connected to a system RAM and a plurality of I/O devices; an operating system stored in the RAM; a power management system stored in the RAM; a power management override system stored in the RAM, the override system including a user flag and a system flag, and operable to override the power management system to disable power management functions with respect to the CPU only, without disabling power management functions with respect to the I/O devices. 